The present invention relates, in general, to the field of integrated circuit devices incorporating semiconductor memory components such as static random access memory (xe2x80x9cSRAMxe2x80x9d), dynamic random access memory (xe2x80x9cDRAMxe2x80x9d), electrically programmable read only memory (xe2x80x9cEPROMxe2x80x9d), ferroelectric random access memory (xe2x80x9cFRAMxe2x80x9d), Flash memory and the like. More particularly, the present invention relates to a multi-bank memory array architecture utilizing topologically non-uniform blocks of sub-arrays and input/output (xe2x80x9cI/Oxe2x80x9d) assignments in an integrated circuit memory device.
Many types of relative large, commodity memory devices are currently available including those types listed above. Regardless of configuration, the primary purpose of the memory device is to store data. Functionally, data may be written to the memory, read from it and, in the case of dynamic random access memory, periodically refreshed to maintain the integrity of the stored data. Each cell of a memory array serves to store a value or charge representative of either a logic level xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d.
In the design of semiconductor memories, the memory cells are typically arranged into sub-arrays with row select circuitry on one side of the sub-arrays and data sensing circuitry on the two sides orthogonal to the row select circuitry. The overall memory is, in turn, built up into multiple banks of multiple sub-arrays in a uniform arrangement. However, such an arrangement serves to constrain the overall integrated circuit chip to then be of certain dimensions in the xe2x80x9cXxe2x80x9d and xe2x80x9cYxe2x80x9d directions as determined by the size of the sub-arrays and the uniform arrangement of the sub-arrays into memory banks. While these constraints may not necessarily present a problem, there are instances where, for a given technology and package definition, they can present a problem.
A presentation and paper given at the 2002 International Solid State Circuits Conference (xe2x80x9cISSCCxe2x80x9d) entitled: xe2x80x9cThe On-Chip 3 MB Subarray Based 3rd Level Cache on an Itanium(trademark) Microprocessorxe2x80x9d by Don Weiss, John J. Wuu and Victor Chin describes a technique for utilizing multiple memory sub-arrays to build up the SRAM cache memory in a microprocessor through the use of a non-uniform sub-array placement. The so-called sub-arrays therein contemplated are specially designed, complete and relatively small SRAMs and each xe2x80x9csub-arrayxe2x80x9d is dedicated to specific memory output bits, e.g. bits 0-7, with all of those specific bits (0-7) stored in the same xe2x80x9csub-arrayxe2x80x9d.
In contrast, with large commodity memory devices, it is simply not practical to have a single sub-array store all occurrences of specific memory output bits. In these types of devices, multiple sub-arrays are required. The design presented in the foregoing ISSCC description is intended for embedded microprocessor memory and is decidedly not a multi-bank design for use in packaged memory products with the associated size and pad placement constraints such designs impose.
Disclosed herein is a multi-bank memory array architecture utilizing topologically non-uniform blocks of sub-arrays and I/O assignments. By using non-uniform blocks of multiple identical sub-arrays, non-uniform assignments of blocks to banks and/or non-uniform assignments of I/Os to blocks, it is possible to optimize the dimensions of the chip and the placement of the I/Os with respect to the package pads. In this manner, the granularity of the building blocks comprising multiple sub-arrays is improved while the flexibility in I/O assignment is also improved leading to more efficient and flexible chip layouts.
Particularly disclosed herein is an integrated circuit memory device which comprises a memory array having at least one memory bank. The memory bank, in turn, comprises a plurality of blocks of sub-arrays wherein at least one of the plurality of blocks of sub-arrays is topologically non-uniform with respect to others of the blocks.
Further disclosed herein is a method for organizing a memory array layout in an integrated circuit device. The method comprises: partitioning the memory array into a plurality of blocks of sub-arrays with at least one of the blocks being topologically non-uniform with respect to others and arranging the plurality of blocks of sub-arrays such that data bit locations assigned to respective ones of the blocks of sub-arrays are substantially proximate to corresponding input/output lines of the memory array.
Still further disclosed herein is an integrated circuit memory device comprising an array of memory cells formed into a plurality of memory banks. The memory device comprises at least one memory bank, with the memory bank further comprising a block of sub-arrays of the memory cells having a first on-chip area. At least one other memory bank comprises two or more additional blocks of sub-arrays of the memory cells, with each of the additional blocks of sub-arrays having a lesser on-chip area than the first on-chip area.